COMMENT ⊗   VALID 00002 PAGES
C REC  PAGE   DESCRIPTION
C00001 00001
C00002 00002	.require "ltr" source_file
C00006 ENDMK
C⊗;
.require "ltr" source_file;
.ltr Mr. John J. Ducey
Resident Representative, O.N.R.
Room 165, Durand Building
Stanford University
Stanford, California 94305

.fac
%3Subject:%1 Capital Equipment Fabrication (Contract DAHC15-73-C-0435)

%3References:%1

1.  L. Earnest (Stanford), "Computer Equipment Purchase (SD-183 Capital
Equipment", letter to DSS-W, 27 March 1973.

2.  R. W. Beard (ARPA), "Approval of ADPE Purchase -- ARPA Order 457",
memo for Director, IPT, 15 May 1973.


Dear Mr. Ducey:

This is a request for approval to fabricate a mechanical arm and a
computer memory interface at a total cost of $22,000.  These items
are required to perform the subject contract (ARPA order number 2494),
but the University is unable to provide funds from its own resources
to procure them.  There are sufficient funds available under the
existing contract to cover these costs.

.cb Mechanical Arm

In order to carry out advanced automation research, we require a second
electric arm similar to the one designed and built here earlier by
Victor Scheinman.  It is to be used, for example, in experimental
two-handed assembly tasks, such as the installation of a hinge.  There
are no suitable arms available commercially.  The cost of this item
is about $8,000.

.cb Memory Interface

.OI
A computer memory interface is needed to connect our recently-acquired
Intel MOS memory (3*65K*18 bits, 500 ns cycle) to other elements of the
Realtime system.  Approval for acquisition of the basic elements of this
system was requested and approved under our earlier contract (SD-183, see
References 1 and 2).  The system has been partially assembled using a
simple <ad hoc> memory interface that permits access to part of the memory.

.skip to column 1
The memory interface is to include error detection/correction capability
and will have an effective bandwidth exceeding 200 million bits/second.
It will interface 3 memory modules (expandable to 8) to 4 devices (expandable
to 8).  There is no commercially available equipment performing this function,
so we must fabricate it.  Total cost is estimated at $14,000.


Forms DD1419 are enclosed for DIPEC clearence on the memory interface.


.lde
.skip 2
cc:  S. Crocker, A. Blue (ARPA)